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preliminary SN9C102 1 ver. 0.9 jan,2002 pc camera controller 1. general description the SN9C102 is a single - chip backend processor to pair with the resolution of vga or cif cmos image sensor. it reads the 9 or 8 bits input raw image data ( rgb bayer pattern) from an image capturing d evice and outputs through a usb port into the pc. this chip includes three individual digital color gains setting (named r, g, b gains), an image compression engine, an offset compensation, a hardware windowing with random image size selection, panning a nd scaling functions. its multi - powerful functions and special architecture make this chip suitable for extra low cost usb pc camera application. 2. features - 9 - bit cmos image raw data input - up to 30fps @ cif, 12fps @vga for pc mode video - provide individual r/g/b digital color gains control - provide snapshoot function - support pixel offset compensation - s upport ic - media , elecvi sion , tas c, hynix , pixart ?etc - embedded two modes of ae calculation and report - provide hardware windowing, 1/2, 1/4 scalin g function and panning function - support operation mode in image quality/frame rate selection - usb 1.1 comp liance and support suspend mode - usb 4 endpoints: control, isochronous read, bulk read, and bulk wr ite endpoints - support video data transfer either in usb isochronous or bulk modes - up to 9 alternated setti ng for usb isochronous transfer - up to 64 various p_id in default mode and random setting the p_id, v_id streaming - 12mhz crystal and 3.3volt only - 4 8 pins l qfp package for normal function www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary SN9C102 2 ver. 0.9 jan,2002 3. pin description number name i/o description 1 nc 2 pid_sel5 i product id selection 3 pid_sel4 i product id selection 4 pid_sel3 i product id selection 5 pid_sel2 i product id selection 6 pid_sel1 i product id selection 7 pid_sel0 i product id selection 8 key i key input 9 rst i chip reset 10 nc 11 nc 12 avdd p vdd for analog part 13 av ss p gnd for analog part 14 tavss p gnd for usb part 15 dn b d - for usb 16 dp b d+ for usb 17 tavdd p vdd for usb part 18 gpio_0 b general purpose i/o 19 gpio_1 b general purpose i/o 20 test i test mode 21 s_pwr_dn o power down for sensor 22 led o led output 23 vdd p vdd for core 24 gnd p gnd for core 25 sda b i2c data 26 scl o i2c clock 27 s_pck b sensor pixel clock 28 vdd p vdd for core 29 gnd p gnd for core 30 sen_clk o sensor clock 31 s_vsync b sensor vsync 32 s_hsync b sensor hsync 33 s_img0 b sensor imag e data 34 s_img1 b sensor image data 35 s_img2 b sensor image data 36 s_img3 b sensor image data www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary SN9C102 3 ver. 0.9 jan,2002 37 vdd p vdd for core 38 gnd p gnd for core 39 s_img4 b sensor image data 40 s _img5 b sensor image data 41 s_img6 b sensor image data 42 s_img7 b sensor image data 43 s_img8 b sensor image data 44 vddap p vdd for pll 45 xin i osc input 46 xout b osc output 47 vssap p gnd for pll 48 nc # i : input pin , o : output pin , b : bi _ direction pin , p : power pin . www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary SN9C102 4 ver. 0.9 jan,2002 4. electrical characteristics 4.1 dc operating condition a. absolute maximum ratings: symbol parameter rating units vcc power supply - 0.3 to 3.6 v vin input voltage - 0.3 to vcc+0.3 v vout output voltage - 0.3 to vcc+0.3 v tstg storage temperature - 55 to 150 c b. recommended operating conditions: symbol parameter min typ max units vcc power supply 3.0 3.3 3.6 v vin input voltage 0 vcc v topr operating temperature 0 70 c c. dc ele ctrical characteristics: (under recommended operating conditions and vcc=3.0 ~ 3.6v , tj=0 to +115 c ) symbol parameter conditions min typ max units vil input low voltage cmos - 0.3 0.3vcc v vih input high voltage cmos 0.7vcc vcc+0.3 v vil input lo w voltage ttl - 0.3 0.8 v vih input high voltage ttl 2.0 5.3 v iil input low current no pull - up or pull - down - 1 1 ua iih input high current no pull - up or pull - down - 1 1 ua ioz tri - state leakage current - 1 1 ua vil schmitt input low voltage cmos 1.20 v vih schmitt input high voltage cmos 2.10 v vol output low voltage iol=4ma 0.4 v voh output high voltage ioh=4ma 2.4 v cin input capacitance 2.8 pf cout output capacitance 2.7 4.9 pf cbid bi - directional buffer capacitance 2.7 4.9 pf 4.2 ac operating condition symbol description max operation frequency notes sen_clk sensor clock 48mhz xin crystal input clock 12 mhz sck i2c clock frequency 400khz www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary SN9C102 5 ver. 0.9 jan,2002 5. usb interface 5.1 endpoint description endpoint # function transfer ty pe maxpsz (byte) 0 std commands control 64 1 iso read isochronous 0, 128, 256, 384, 512, 680, 800, 900, 1023 2 bulk read bulk 64 3 interrupt read interrupt 1 5.2 descriptor table data device 12 01 10 01 00 00 00 40 vl vh pl ph 01 01 00 01 00 01 co nfiguration 09 02 17 01 01 01 00 80 fa string 16 03 55 00 53 00 42 00 20 00 63 00 61 00 6d 00 65 00 72 00 61 00 alternate setting = 0 interface 0 09 04 00 00 03 ff ff ff 00 endpoint 1 07 05 81 01 00 00 01 endpoint 2 07 05 82 02 40 00 00 endpoint 3 07 05 83 03 01 00 64 alternate setting = 1 interface 0 09 04 00 01 03 ff ff ff 00 endpoint 1 07 05 81 01 80 00 01 endpoint 2 07 05 82 02 40 00 00 endpoint 3 07 05 83 03 01 00 64 alternate setting = 2 interface 0 09 04 00 02 03 ff ff ff 00 endpoint 1 07 05 81 01 00 01 01 endpoint 2 07 05 82 02 40 00 00 endpoint 3 07 05 83 03 01 00 64 alternate setting = 3 interface 0 09 04 00 03 03 ff ff ff 00 endpoint 1 07 05 81 01 80 01 01 endpoint 2 07 05 82 02 40 00 00 endpoint 3 07 05 83 03 01 00 64 altern ate setting = 4 interface 0 09 04 00 04 03 ff ff ff 00 endpoint 1 07 05 81 01 00 02 01 endpoint 2 07 05 82 02 40 00 00 endpoint 3 07 05 83 03 01 00 64 alternate setting = 5 interface 0 09 04 00 05 03 ff ff ff 00 endpoint 1 07 05 81 01 a8 02 01 endp oint 2 07 05 82 02 40 00 00 www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary SN9C102 6 ver. 0.9 jan,2002 endpoint 3 07 05 83 03 01 00 64 alternate setting = 6 interface 0 09 04 00 06 03 ff ff ff 00 endpoint 1 07 05 81 01 20 03 01 endpoint 2 07 05 82 02 40 00 00 endpoint 3 07 05 83 03 01 00 64 alternate setting = 7 interface 0 09 04 00 07 03 ff ff ff 00 endpoint 1 07 05 81 01 84 03 01 endpoint 2 07 05 82 02 40 00 00 endpoint 3 07 05 83 03 01 00 64 alternate setting = 8 interface 0 09 04 00 08 03 ff ff ff 00 endpoint 1 07 05 81 01 ff 03 01 endpoint 2 07 05 82 02 40 00 0 0 endpoint 3 07 05 83 03 01 00 64 www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary SN9C102 7 ver. 0.9 jan,2002 6. serial control interface the SN9C102 supports i2c tm - bus transfer protocol and is act ing as a master device. it supports receiving and transmitting speed of 100khz and 400khz (note: downloading from eeprom when power on requires speed of 400khz.) 6.1 serial bus overview only two wires sda (serial data) and scl (serial clock) are needed t o carry information between the devices connected to the serial bus. normally both sda and scl lines are open - collector structures and pulled high by external pull - up resistors. only the master can initiates a transfer (start), generates clock signals, an d terminates a transfer (stop). start and stop condition: a high to low transition of the sda line while scl is high defines a start condition. a low to high transition of the sda line while scl is high defines a stop condition. valid data: the data on the sda line must be stable during the high period of the scl clock. within each byte, msb is always transferred first. read/write control bit is the lsb of the first byte. both the master and slave can transmit and receive data through the serial bus. acknow ledge: the receiving device should pull down the sda line during high period of the scl clock line when a complete byte was transfer by transmitter. in the case of a master received data from a slave, the master does not generate an acknowledgment on the l ast byte to indicate the end of a master read cycle. 6.2 data transfer format master device transmits data to slave device (write cycle) s : start a : acknowledgement from slave device. p : stop r/w : the lsb of 1st byte decides the current cycle is rea d or write. r/w=1 read ;r/w=0 write. slave address : serial slave device address. sub address : the slave device control register address. during write cycle, the master device(sonix?s pc camera controller) generates start condition and the n place the 1 st byte data which contains slave address (7 bits) and the s slave address (7 bits) 0 a sub_address (8 bit) 1st byte 2nd byte a p data (8 bit) a 3rd byte master transmits and slave receives(write) www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary SN9C102 8 ver. 0.9 jan,2002 read/write control bit onto sda line. after slave device issues an acknowledgment, the master places the 2 nd byte (sub - address data) data onto sda line. and then followed the slave ack nowledgment, the master places the 8 bits data on sda line and transmits to slave device control register (address was assigned by 2 nd byte). after slave issues an acknowledgment, the SN9C102 can generate a stop condition to end this write cycle. this chip only supports 8 bytes multiple write function. that is, master can write only 8 contineous address data into slave device. slave device transmits data to master device (read cycle) the read cycle of the SN9C102 has 2 phases, dummy write phase and read ph ase. note, this SN9C102 supports single read only. that is, one dummy write phase plus one read phase can get only one byte data from slave device internal register. a. the 1st phase (dummy write phase): the dummy write phase is the same as the general serial write. the only difference is the write data is the address of the register. the sub - address is the register address inside the slave device b. the 2nd phase (read phase) : the SN9C102 generates star t condition and then place the 1 st byte data, which contains slave address (7 bits) and a read/write control bit onto sda line. after salve device issues an acknowledgment, the 8 bits data coming from slave device internal register will be placed onto the sda line serially. the address of the 8 bit data was assigned by previous dummy write cycle. note, there is no acknowledgement issued by master device. master transmits and slave receives (dummy write cycle) s slave address (7 bits) 0 a sub address (8 bit) 1st byte 2nd byte a p master receives and slave transmits (read cycle) s slave address (7 bits) 0 a data (8 bit) 1st byte 2nd byte 1 p no ack from master www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary SN9C102 9 ver. 0.9 jan,2002 7. register description address bit r/w name description 0(00h) 7:0 r asic_id[7:0] sonix p c cam chip id (re turn 10h) 0 r/w s_pwr_dn 1: power down for sensor 1 r/w s_pdn_inv 1: inverse pin s_pwr_dn 2 r/w v_tx_en 1: video transfer enable 3 r/w led output to pin led 4 r key read pin key 5 reserve 6 r/w sys_sel_24m 1: system clock select 24mhz (fsys_clk = 24 mhz) 0: system clock select 12mhz (fsys _clk= 12 mhz) 1 (01h) 7 r/w test_asic 1: test mode enable for testing asic. note: don?t enable it 1:0 r/w gpio[1:0] general purpose i/o 2 7:2 reserve 3 - 7 7:0 reserve 0 r/w i2c_high 1: i2c interface is high speed (400k hz ). 0: i2c interface is low speed (100k hz ). 1 r/w i2c_sel_rd 1: select i2c read mode . 0: select i2c write mode . 2 r i2c_rdy 1: ready for i2c read/write. 0: busy for i2c read/write. 3 r i2c_err i2c interface is error when rea d/write. 6:4 r/w i2c_byte_num[2:0] i2c read/write byte number. 8 (08h) 7 r/w i2c_dev 1: sensor interface is i2c. 0: sensor interface is 3 - wire interface. 6:0 r/w slave_id[6:0] i2c slave id 9 (09h) 7 reserve 10 - 14 (0a - 0eh) 7:0 r/w i2c_data[7:0] register r ead/write address and data port for i2c device note: write: you must write 5 bytes to it at one time. the first data is register address, the other data are data0, data1, data2 and data3. read: you must read 5 bytes from it at one time. the sequence are da ta0, data1, data2, data3 and data4. 15 (0fh) 7:0 r/w c ontrol / status register c ontrol and status report byte 3:0 r/w r_gain[3:0] red channel g ain control. gain = (1+r_gain/8) note: it is sync with vsync 16 (10h) 7:4 r/w b_gain[3:0] blue channel gain control. gain = (1+b_gain/8) note: it is sync with vsync www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary SN9C102 10 ver. 0.9 jan,2002 3:0 r/w g_gain[3:0] green channel gain control. gain = (1+g_gain/8) note: it is sync wit h vsync 17 (11h) 7:4 reserve 18 (12h) 7:0 r/w h_start[7:0] start active pixel number after h - sync of sensor note: the 1 st line sequence of image data is bgbgbg the 2 nd line sequence of image data is grgrgr 19 (13h) 7:0 r/w v_start[7:0] s tart active line number after v - sync of sensor 20 (14h) 7:0 r/w offset[7:0] offset adjustment for sensor image data. 5:0 r/w h_size[5:0] horizontal pixel number for sensor. 21 (15h) 7:6 reserve 4:0 r/w v_size[4:0] vertical pixel number for sensor. 22 (16h) 7:5 reserve 0 r/w lq_sel 1: low quality for compression mode 0: high quality for compression mode 1 reserve 3:2 r/w sen_rate sen sor master clock frequency control 11: 48 mhz 10: 24 mhz 01: 12 mhz (default) 00: fsys _clk /mck_size 4 r/w test_img 1: image data is at test mode 5 r/w sen_clk_en 1: enable sensor clock. (output to low) 6 r/w sen_clk_inv 1: inverse sen_clk 23 (17h) 7 rese rve 0 r/w pck_ris 1: image data latch at rising edge of sensor pck 0: image data latch at falling edge of sensor pck 1 r/w hsync_ris 1: change line at rising edge of hsync 0: change line at falling edge of hsync 2 r/w vsync_ris 1: change fra me at rising edge of vsync 0: change frame at falling edge of vsync 3 r/w vsync_high 1: vsync are high active. 0: vsync are low active. 5:4 r/w scal[1:0] resolution of sub - sampling before compression 00: 1/1 (640*480), (352*288) 01: 1/2 (320*240), (176*144) 1x: 1/4 (160*120), (88*72) 6 r/w sel_curve 0: normal curve 1: use companding curve 24 (18h) 7 r/w cmp_mode compression mode selection: 0: no compression for image data 1: compression enable www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary SN9C102 11 ver. 0.9 jan,2002 0 r/w sync _ out 0: sensor sync timing output disa ble. (sensor is master mode) 1: sensor sync timing output enable(sensor is slave mode) 1 r/w pck_out 0: pixel clock input from pin ?pck?. 1: pck_data output to pin ?pck? and internal pck is input from sensor master clock. 2 reserve 3 r/w pck_2x 1: pixel clock period is 2 x master clock period. 0: pixel clock period is 1 x master clock period. note: it is valid when pck_out=?1? 25 (19h) 7:4 r/w mck_size[3:0] sensor master clock period size when sen_rate=0. (mck_size range is from 2 to 15) note: output freq uency of master clock=( fsys _clk /mck_size) 5:0 r/w ho_size[5:0] horizontal pixel number for sensor. (one unit is 32 pixels) note: it is sync with vsync 26 (1ah) 7:6 reserve 4:0 r/w vo_size[4:0] vertical pixel number for sensor. (one unit i s 32 lines) note: it is sync with vsync 27 (1bh) 7:5 reserve 2:0 r/w ae_strx[2:0] start horizontal pixel for ae in active window. (one unit: 32 pixels) 28 (1ch) 7:3 reserve 2:0 r/w ae_stry[2:0] start vertical line for ae in active window. (one un it: 32 pixels) 29 (1dh) 7:3 reserve 4:0 r/w ae_endx[4:0] end horizontal pixel for ae in active window. (one unit: 32 pixels) 30 (1eh) 7:5 reserve 3:0 r/w ae_endy[3:0] end vertical line for ae in active window. (one unit: 32 pixels) 31 (1fh) 7:4 reserve www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary SN9C102 12 ver. 0.9 jan,2002 8. application circuit www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary SN9C102 13 ver. 0.9 jan,2002 9. package dimension l 48pin lqfp a detail view a 0.2 max. 1.0 ref. 1.4 7 x max. 9.0 ? 0.2 9.0 ? 0.2 0.50 typ. 7.00 ? 0.1 0.10 (all dimensions are in millimeters) 1 48 1.6 max. 0.6 ? 0.15 0.22 ? 0.05 12 13 24 25 36 37 www.datasheet.co.kr datasheet pdf - http://www..net/

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